The present invention has been developed in response to a long existing need for packaging high density optical, fluidic or electronic equipment, and further, in response to the need for an interconnection technique suitable for miniaturization, automatic assembly and acceptance of either shielded or unshielded transmission lines in a network suitable for conveying information in the form of high frequency components.
The increased requirement for miniaturization, when coupled with the complexity of circuitry employing very high frequency components and systems, provides a challenging requirement for a new technique of circuit interconnection enabling completion of a sophisticated electronic system within a smallest possible package. The trend in integrated circuits toward creation of multi-function chips results in an ever increasing availability of new chips which greatly increases the number of required interconnections in a wiring network or package, and which necessitates quickly and easily accomplished changes in existing packages for acceptance of the newly available chips.
Increased signal frequencies and rates of information transfer, and decreased circuit noise tolerance have necessitated a revision in interconnection requirements. For the circuit standpoint, the interconnection lines must reduce propagation time delay, and keep at acceptable levels generated electrical reflections, cross talk signals, common ground return path signals and signal attenuation. False signals or noise, and signal attenuation levels are reduced by control of characteristic impedance and shielding of the transmission lines. Propagation delay is reduced by use of minimum transmission line lengths. However, as the need for low amplitude-short rise time signals increases, there results an increasing network sensitivity to noise and transmission losses. Thus the trend toward miniaturization, high speed and higher density, results in diminishing available space for interconnections coupled with an increased number of interconnections with reduced sensitivity to interference and signal attenuation.
Another of the problems encountered in design of an interconnection system, is the capability of performing engineering changes. The trend in integrated circuits toward multi-function circuits per chip, as well as advancing technology in multi-function circuitry fabrication, often requires total redesign of a package to accept improved and newly available chips and to eliminate obsoleted chips. A desirable interconnection system thereby should be easily adapted for change, either without considerable redesign, or with complete replacement with an interconnection system which is easy to design and fabricate at low cost.
In an attempt to meet the requirements of miniaturized interconnection systems, considerable effort has been expended in the prior art toward termination of discrete coaxial cables. Heretofore, such efforts have produced insufficient results, especially in adapting packaging techniques for automation and low cost in both network design and fabrication.
According to another prior art packaging technique, the leads of a microelectronic component are received in the apertures of a prepunched terminal board. The apertures receiving the leads also contain insulation covered wiring threaded up through the apertures. The wiring is also threaded down through adjacent apertures of the board to provide a laced function and appearance. Soldering of the laced wires to the leads is done directly through the wire insulation, the molten solder melting the wire insulation, generally wicking into and filling the holes, and electrically bonding the wiring to the leads. This technique is disadvantageous since all the wiring and solder bonding must be done by hand. Great care must be undertaken to prevent solder leakage paths on other wiring or on other surfaces of the substrate. It is also difficult to change circuitry, since such would involve drilling out or reflowing the solder connections, with the result that the solder is either particulated and scattered, or is reduced to a molten state for flowing into undesired apertures or on other surfaces of the terminal board, causing contamination and electrical shorting of the unchanged circuitry. In addition, the system is not suited for shielded wire interconnections because the solder bonded to the microelectronic component leads in selected apertures would create leakage paths to the shielded portions of the wire.
According to another prior art technique, insulated wiring is adhesively bonded to a substrate surface, the wiring forming a criss-cross matrix of discrete electrical paths. Holes are drilled in the substrate at selected locations to expose the wiring conductors. The holes are then plated or otherwise lined with a conducting material, thereby providing electrical sockets, in contact with the wiring conductors and for receiving the leads of microelectronic components. This packaging technique requires considerable expenditures of time because of the need for separately drilling and electrically connecting each socket. In addition, this system cannot be adapted for shielded wiring, since the drilling and plating operations would create electrical shorting paths to the shielding provided on the wiring. Since the matrix of wiring is adhesively bonded to the substrate, and since discrete paths of wiring overlie one another on the matrix surface, changes in point-to-point interconnections is difficult. To change the network, the wiring connected to the sockets must be severed and then patched with an additional length of wiring, followed by covering the patched portions with insulation. Such operation changes the characteristic impedance of the circuit paths.
Another interconnection technique has resulted in a multi-layer printed circuit, wherein several layers of deposited copper conductors result in increased density. However, a requirement for precision, in masking, in registration between layers, in hole drilling and interconnection between layers, requires a large investment in automated production machinery. In addition, computer usage is required for even the most basic network design, as well as for the choice of layers and point-to-point destinations for each conductor. Since deposited conductors are used, the system is not well suited for fabrication of precisely controlled characteristic impedance conductors. In addition, an entire circuit must be redesigned to accommodate the smallest circuitry change. Another major drawback of such a packaging technique results from the need to build completely the multilayer package before testing it for deficiencies in cross talk, attenuation, reflection noise and common ground return path noise. Should such deficiencies in performance occur, a complete redesign of the package is required.